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Si4313-B1
Frequency mistuning caused by crystal inaccuracies can be compensated by enabling the digital automatic
frequency control (AFC) in receive mode.
5.6. Synthesizer
An integrated Sigma Delta ( ?? ) Fractional-N PLL synthesizer capable of operating from 240–960 MHz is provided
on-chip. Using a ?? synthesizer has many advantages; it provides flexibility in choosing data rate, deviation,
channel frequency, and channel spacing.
The PLL and ?? modulator scheme is designed to support any desired frequency and channel spacing in the range
from 240–960 MHz with a frequency resolution of 156.25 Hz (Low band) or 312.5 Hz (High band).
?
Table 11. PLL Synthesizer Block Diagram
The reference frequency to the PLL is 10 MHz. The PLL utilizes a differential L-C VCO with integrated on-chip
inductors. The output of the VCO is followed by a configurable divider that divides down the signal to the desired
output frequency band. The modulus of this divider stage is controlled dynamically by the output from the ??
modulator. The tuning resolution is sufficient to tune to the commanded frequency with a maximum accuracy of
312.5 Hz anywhere in the range between 240–960 MHz.
5.6.1. VCO
The output of the VCO is automatically divided down to the correct output frequency depending on the hbsel and
fb[4:0] fields in "Register 75h. Frequency Band Select". In receive mode, the LO frequency is automatically shifted
downwards by the IF frequency of 937.5 kHz, allowing receive operation on the same frequency. The VCO
integrates the resonator inductor and tuning varactor; so, no external VCO components are required.
The VCO uses a capacitance bank to cover the wide frequency range specified. The capacitance bank will
automatically be calibrated every time the synthesizer is enabled. In certain fast hopping applications, this might
not be desirable; so, the VCO calibration may be skipped by setting the appropriate register.
5.7. Crystal Oscillator
The Si4313 includes an integrated 30 MHz crystal oscillator with a fast start-up time of less than 600 μs when a
suitable parallel resonant crystal is used. The design is differential with the required crystal load capacitance
integrated on-chip to minimize the number of external components. By default, all that is required off-chip is the
30 MHz crystal.
The crystal load capacitance can be digitally programmed to accommodate crystals with various load capacitance
requirements and to adjust the frequency of the crystal oscillator. The tuning of the crystal load capacitance is
programmed through the xlc[6:0] field of "Register 09h. 30 MHz Crystal Oscillator Load Capacitance." The total
internal capacitance is 12.5 pF and is adjustable in approximately 127 steps (97fF/step). The xtalshift bit provides a
coarse shift in frequency but is not binary with xlc[6:0].
The crystal frequency adjustment can be used to compensate for crystal production tolerances. Utilizing the on-
chip temperature sensor and suitable control software, the temperature dependency of the crystal can be
canceled.
Rev. 1.0
27
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